The present invention relates to methods and devices for verifying and correcting data resulting from analog to digital conversion through a so-called successive approximation technique, employing an analog-digital converter (ADC) liable to introduce an error of a certain entity because of the process spread or of other imprecisions in its circuit.
Analog-to-digital converters (ADC) are of fundamental importance in control, regulation, data collection and processing systems. They constitute conversion interfaces of analog entities (real-world parameters) into digital data that can be easily processed by digital circuits, such as combinative logic networks, memories, microprocessors and the like. Among these, analog-to-digital converters (ADC) that are based on successive approximation steps cover a large portion of applications.
In successive approximation ADCs, an analog input voltage is compared with a voltage that is synthesized by an internal digital-to-analog converter (DAC) contained within the ADC converter. A digital input to said internal DAC is provided by a register (SAR) that stores the current digital value of the successive approximation process, which is updated step by step depending on the result of the last comparison carried out. After a number of comparisons (which may be equal to or greater than the number of bits handled by the converter), the data stored in the SAR register represents the digital result of the completed conversion.
Commonly, at the start of any new conversion process, a certain code or digital value, for example 100.multidot..multidot..multidot.0, that may represent the intermediate code (value or digital data) as referred to the range of convertible digital values, is provided to the internal DAC. This is effected by "setting" the SAR to such an intermediate value. The result of a first comparison will define the successive content of the SAR which may become for example either 110.multidot..multidot..multidot.0 or 0100.multidot..multidot..multidot.0, and therefore, through successive bisections, the code or digital data that represents the converted input analog value will be reached, within the theoretical approximation limit defined by the number of bits of the converter.
FIG. 1 is a functional diagram of a successive approximation ADC. As may be observed, the internal DAC may be constituted by an array of capacitances: C, C/2, C/4, C/8 and C/16, that performs a capacitive partition of a reference voltage VREF in order to produce an analog value corresponding to the digital code stored in the SAR.
Practically, a capacitance is associated with each bit of the SAR, the capacitance associated with the first bit (MSB or Most Significant Bit) is twice the capacitance that is associated with the second bit, which is twice the capacitance associated with the third bit and so forth, until the so-called LSB (Least Significant Bit). Therefore the analog value produced by the code 0100.multidot..multidot..multidot.0 is double the value that would be produced with the digital code 0010.multidot..multidot..multidot.0 and half the value corresponding to the code 1000.multidot..multidot..multidot.0.
A main cause of problems in this type of converter is capacitive mismatching, that is an imprecise ratio among the values of the various capacitances that compose the internal DAC, which causes an incorrect conversion of the current digital value stored in the SAR register in an analog value (by capacitive partitioning of a VREF).
The capacitance per unit area of an integrated circuit capacitor is fairly unpredictable. This is because the capacitance is sensitively affected by such factors as the background doping, the degree of drive performed for well doping, the location of the peak of any VT-adjust implant, the exact thickness of the gate oxide, and the density of fixed charge in the oxide and at the oxide interfaces, etc.
In addition, the capacitance of an integrated circuit capacitor will not be a strictly linear function of the capacitor's designed area. This is true for several reasons. First, the capacitance is determined not only by the homogeneous area in the center of the capacitor plate, but also by the trenching areas at the perimeter of the capacitor plate. These perimeter elements do not scale with area, but rather linearly (i.e. as the square root of area). Moreover, the importance of these perimeter capacitances in relation to the central capacitances may itself be affected by the process variable mentioned above. Moreover, the capacitances at the corners of a rectangular capacitor will themselves scale differently from the straight-line perimeter capacitance. Moreover, line-width variation in processing will also affect the areas of different capacitors differently.
For example, it may occur that, because of an incorrect ratio of capacitances between the various capacitors that compose the internal DAC, the voltage level or analog value that is associated with a digital code, e.g. 100.multidot..multidot..multidot.0, is lower than the analog value corresponding to the digital code 011.multidot..multidot..multidot.1.
In such a situation, a so-called "missing code" phenomenon occurs, that is the digital code 011.multidot..multidot..multidot.1 will never be converted by the internal DAC. Such an operating condition, that may be due to process variation or to some other defect that may have altered the correct design capacitance ratio, is illustrated in FIG. 2B by direct comparison with a correct operating condition illustrated in FIG. 2A. For simplifying the illustration, the schemes refer to the case of a three-bit converter (that is every conversion implies the execution of three comparisons), and show three distinct conversion processes for three different values or codes (010, 011 and 100) representing three different levels in a voltage scale from 0 V to 5 V (as schematically depicted on the right hand side of the conversion schemes). In the case shown in FIG. 2B, the occurrence of a capacitive mismatching causing an impossibility of converting correctly the code 011 by the internal DAC is shown.
Of course, it may also occur that the so-converted level 100.multidot..multidot..multidot.0 is lower than the level 011.multidot..multidot..multidot.10, that is the mismatching of the capacitance ratio may be so marked as to cause the disabling of two adjacent digital codes (values) or even more.
Various remedies have been studied and proposed for recovering the functionality of complex integrated circuits containing one or more ADC converters that have revealed themselves defective in the above-noted manner. This has been achieved by suitably modifying the operating characteristic of the internal DAC that has been recognized as defective through a series of specific functionality tests, by the use of dedicated analog circuits (amplifiers, track-and-hold circuits and the like, associated with EPROMs that may be programmed through a correction test and trimming process, and/or ROMs). These known correction systems are relatively complex and greatly penalize the economy of the whole integrated circuit.
Digital correction techniques, based on the generation of redundant codes that may be employed for effecting a digital correction capable of re-establishing the functionality of the internal DAC are also known. These correction systems, though not requiring the integration of analog circuits, require the use of RAM and/or EPROM memories capable of storing the necessary information for performing one or more correction procedures during the conversion process. As an alternative to the use of dedicated memories, the correction may also be performed automatically, by the use of an appropriate algorithm, in function of the redundant bits that are generated.
In general, the procedures for detecting missing codes and for correcting a defective converter are relatively complex and require the realization of arrays of trimming elements or the use of a plurality of internal DACs and memories.
The volume: "Design of CMOS Analog Integrated Circuits" by F. Maloberti, 1986, Section 8, pages 37-60, contains a brief description of various correction techniques. Several of these techniques also permit reduction of the so-called unadjusted total error (TUE), which accounts also for the input offset of the ADC converter.
In a large number of integrated devices containing successive approximation ADCs, e.g. in many microcontrollers, the device specifications may not be particularly stringent as far as TUE is concerned; for example they may accept a TUE equal to .+-.2LSB, but they are typically intolerant of missing codes.
Moreover, by analyzing the causes that determined the rejection of a certain percentage of fabricated devices, it may be found that for about 90% of the rejected devices, the cause consisted of a missing code. By analyzing further the rejected devices, a typical "breakdown" of causes may reveal that about 60-70% of the rejections are due to a single missing code occurrence, about 28-38% of rejects are due to the presence of a double missing code, while a residue of about 2% denounces a triple missing code, notwithstanding the fact that a percentage of over 90% of all the rejected devices satisfy the specifications as far as TUE is concerned.
Therefore, there is an evident need and/or utility for a correction method for missing code, imputable to capacitive mismatching in an internal DAC of a successive approximation ADC, easy to implement by employing exclusively logic circuitry, that practically will avoid the rejection of a relatively large percentage of devices because of the occurrence of a missing code, almost exclusively due to capacitive mismatching in the internal DAC, while satisfying the specifications for what concerns the total unadjusted error (TUE).
This objective is fully satisfied by the system of the present invention that can be implemented without requiring the use of memories or of analog circuits for altering the analog structure of the internal DAC. The system of the invention is theoretically capable of correcting also plural missing codes. The eventual choice of implementing in a certain device a "corrector" for a single missing code, for a double missing code or for more than two missing codes, will depend on the yield characteristics of the particular fabrication processes of the device. From the percentages that emerge from an analysis of a typical production, as reported above, it would appear that an optimum design choice would imply the implementation of a corrector, according to the present invention, capable of correcting as far as two adjacent missing codes. This would permit "recovery" to a perfect functionality what would otherwise be, by far, the largest proportion of rejected devices. The occurrence of adjacent missing codes in a number greater than two is statistically not very significant or, whenever it becomes statistically significative, it may almost certainly be an indication that serious problems have occurred in the fabrication process, the occurrence of which would normally tend to bring out of specification limits many other parameters, even less critical than the capacitive mismatching in DACs.
Of course, the correction process of the invention, for example for a double missing code, will require the performing of three further comparisons beyond those necessary to the normal conversion process and, in view of the fact that each comparison requires a certain execution time (for example of about 800 ns), the correction procedure implies an increase of the conversion time of about 2-3 microseconds. On the other hand, it is often the case in microcontrollers that the circuits dedicated to the analog-to-digital conversion be amply "margined", i.e. they are often structurally capable of operating (as stand-alone circuits) correctly at clock frequencies that may be well above those actually used by the system, and, in such a frequent case, it is possible, by suitably modifying the timing signals of the converter, to maintain the same conversion times, without requiring any redesigning of the analog part of the comparator circuit.
The correction process, for the case of implementing a corrector for a single missing code, consists of the following steps:
a) decrementing by an LSB the digital data produced by the conversion process and stored in the SAR; PA1 b) converting the decremented digital value stored in the SAR into an analog value; PA1 c) comparing said converted analog value with the input analog value; PA1 d) incrementing the digital value stored in the SAR by an LSB if the analog value corresponding to the converted digital value is less than said input analog value; PA1 e) using the digital value stored in the SAR as a correct digital result of the analog-digital conversion of said input analog value. PA1 a) decrementing by two LSBs the digital data produced by the conversion process and stored in the SAR; PA1 b) converting the digital data stored in the SAR in an analog value; PA1 c) comparing said converted analog value with the input analog value; PA1 d) incrementing by an LSB the digital value stored in the SAR if the analog value corresponding to the converted digital value is less than said input analog value; PA1 e) repeating the steps b), c) and d); PA1 f) incrementing the digital value stored in the SAR by two LSBs; PA1 g) repeating the steps b) and c); PA1 h) decrementing the digital value stored in the SAR by two LSBs if the analog value corresponding to the converted digital value is greater or equal to said input analog value or decrementing by one LSB the digital value stored in the SAR if the analog value corresponding to the converted digital value is less than said input analog value; PA1 i) using the digital value stored in the SAR as corrected digital result of the analog-digital conversion of said input analog value.
In case of implementing a corrector for a double missing code, the process consists of the following steps: